In conventional digital-to-analog converters (“DACs”), such DACs may be unary, binary, or segmented. A conventional segmented DAC may be thought of as two DACs in one DAC, where most significant bits (“MSBs”) for example are thermometer weighted or coded bits and least significant bits (“LSBs”) are binary weighted. Output of any of these types of DACs may have some error due to timing differences among switches, such as transistors for example, of such DACs.
Accordingly, it would be useful to provide compensation to resolve or reduce timing errors of a DAC to enhance performance.